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» Operating-system directed power reduction
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CISS
2007
IEEE
14 years 1 months ago
Dynamic Resource Allocation for Multi Source-Destination Relay Networks
Abstract—We consider a wireless network consisting of multiple sources communicating with their corresponding destinations utilizing a single half-duplex relay. The goal is to min...
Onur Sahin, Elza Erkip
DAC
2002
ACM
14 years 8 months ago
Scheduler-based DRAM energy management
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...
Victor Delaluz, Anand Sivasubramaniam, Mahmut T. K...
23
Voted
ISPASS
2009
IEEE
14 years 2 months ago
User- and process-driven dynamic voltage and frequency scaling
We describe and evaluate two new, independently-applicable power reduction techniques for power management on processors that support dynamic voltage and frequency scaling (DVFS):...
Bin Lin, Arindam Mallik, Peter A. Dinda, Gokhan Me...
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 21 days ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan