261 search results - page 17 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
VTS
1997
IEEE
14 years 27 days ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
ISQED
2009
IEEE
14 years 3 months ago
2009
IEEE
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...
ITC
1997
IEEE
14 years 27 days ago
1997
IEEE
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
ISPD
1997
ACM
14 years 27 days ago
1997
ACM
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
VTS
2008
IEEE
14 years 3 months ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...