A novel ACO-based pattern generation for peak power estimation in VLSI circuits

Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue of this task is which pattern pair would cause this peak power value. An exhaustive search from all possible combinations is time-consuming and impractical for VLSI circuits with hundreds of inputs. In this paper, a new pattern generation approach with Ant Colony Optimization, which imitates the behavior of ants looking for foods, is proposed for peak power estimation. The approach returns patterns which are highly suspicious to consuming the peak power. The gate delay issue is considered in this work. Furthermore, the valid state issue in sequential circuits is considered as well. Since the real delay value is technology-dependent, these generated patterns of our approach and other approaches are then applied into a commercial power calculation tool, PrimePower, to demonstrate the effectiveness of the approac...

• Type: Conference
• Year: 2009
• Where: ISQED
• Authors: Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang
• Keywords: Hardware, ISQED 2009, Peak Power, Peak Power Estimation, TSMC 0.18 µm