261 search results - page 19 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ISSS
1999
IEEE
14 years 1 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
TCAD
2008
13 years 8 months ago
2008
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
IEEEINTERACT
2003
IEEE
14 years 2 months ago
2003
IEEE
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
FPL
2007
Springer
14 years 18 days ago
2007
Springer
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
ISPD
2010
ACM
14 years 3 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...