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» Optimal Hardware Pattern Generation for Functional BIST
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ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
14 years 7 days ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram
DATE
2006
IEEE
145views Hardware» more  DATE 2006»
14 years 2 months ago
Building a better Boolean matcher and symmetry detector
Boolean matching is a powerful technique that has been used in technology mapping to overcome the limitations of structural pattern matching. The current basis for performing Bool...
Donald Chai, Andreas Kuehlmann
IESS
2007
Springer
156views Hardware» more  IESS 2007»
14 years 2 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
SIGGRAPH
1987
ACM
14 years 6 days ago
Generating antialiased images at low sampling densities
Ray tracing produces point samples of an image from a 3-D model. Constructing an antialiased digital picture from point samples is difficult without resorting to extremely high sa...
Don P. Mitchell
GECCO
2007
Springer
158views Optimization» more  GECCO 2007»
14 years 2 months ago
A novel generative encoding for exploiting neural network sensor and output geometry
A significant problem for evolving artificial neural networks is that the physical arrangement of sensors and effectors is invisible to the evolutionary algorithm. For example,...
David B. D'Ambrosio, Kenneth O. Stanley