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» Optimal Hardware Pattern Generation for Functional BIST
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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
14 years 4 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
14 years 3 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
IPPS
2008
IEEE
14 years 4 months ago
Lattice Boltzmann simulation optimization on leading multicore platforms
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
Samuel Williams, Jonathan Carter, Leonid Oliker, J...
ICDCS
2005
IEEE
14 years 3 months ago
Controlling Gossip Protocol Infection Pattern Using Adaptive Fanout
We propose and evaluate a model for controlling infection patterns defined over rounds or real time in a gossipbased protocol using adaptive fanout. We model three versions of go...
Satish Verma, Wei Tsang Ooi
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
14 years 3 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin