261 search results - page 5 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
VTS
1997
IEEE
13 years 11 months ago
1997
IEEE
Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has se...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
ATS
1998
IEEE
13 years 11 months ago
1998
IEEE
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
ET
2000
13 years 7 months ago
2000
An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum num...