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HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
CONEXT
2006
ACM
14 years 1 months ago
Migrating home agents towards internet-scale mobility deployments
While the IETF standardization process of the Mobile IPv6 and Network Mobility (NEMO) protocols is almost complete, their large-scale deployment is not yet possible. With these te...
Ryuji Wakikawa, Guillaume Valadon, Jun Murai
MOBICOM
2006
ACM
14 years 1 months ago
Routing algorithms for delay-insensitive and delay-sensitive applications in underwater sensor networks
Underwater sensor networks consist of sensors and vehicles deployed to perform collaborative monitoring tasks over a given region. Underwater sensor networks will find applicatio...
Dario Pompili, Tommaso Melodia, Ian F. Akyildiz
ICS
2005
Tsinghua U.
14 years 1 months ago
High performance support of parallel virtual file system (PVFS2) over Quadrics
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda
HPCA
2006
IEEE
14 years 7 months ago
LogTM: log-based transactional memory
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan...