98 search results - page 18 / 20 » Optimal Non-deterministic Functional Logic Computations |
DAC
2010
ACM
13 years 11 months ago
2010
ACM
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
ASAP
2005
IEEE
14 years 19 days ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
JAIR
2008
13 years 7 months ago
2008
Model checking is a promising technology, which has been applied for verification of many hardware and software systems. In this paper, we introduce the concept of model update to...
ASAP
2004
IEEE
13 years 10 months ago
2004
IEEE
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...