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TVLSI
2010
13 years 4 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
TFS
2010
152views Education» more  TFS 2010»
13 years 4 months ago
Robust Optimal Reference-Tracking Design Method for Stochastic Synthetic Biology Systems: T-S Fuzzy Approach
At present, the development in the nascent field of synthetic gene networks is still difficult. Most newly created gene networks are nonfunctioning due to intrinsic parameter fluct...
Bor-Sen Chen, Chih-Hung Wu
ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
13 years 12 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
ETFA
2005
IEEE
14 years 3 months ago
Fuzzy multi-objective optimization for network design of logistic and production systems
Global competition has given rise to Logistic and Production Systems (LPSs), that are distributed manufacturing systems integrating international logistics and information technol...
Mariagrazia Dotoli, Maria Pia Fanti, Agostino Marc...
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Wire sizing with scattering effect for nanoscale interconnection
—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay signifi...
Sean X. Shi, David Z. Pan