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» Optimal instruction scheduling using integer programming
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EGH
2005
Springer
14 years 3 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
14 years 2 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
14 years 6 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
CASES
2006
ACM
14 years 3 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
CASES
2007
ACM
14 years 1 months ago
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter