979 search results - page 42 / 196 » Optimal instruction scheduling using integer programming |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
—Due to increase in demand for reconfigurability in embedded systems, real-time task scheduling is challenged by non-negligible reconfiguration overheads. If such overheads are n...
ICS
1995
Tsinghua U.
14 years 1 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
DAC
2010
ACM
13 years 10 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
CODES
2007
IEEE
14 years 4 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
CC
2006
Springer
14 years 1 months ago
2006
Springer
Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity o...