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» Optimal integrated code generation for VLIW architectures
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CODES
1999
IEEE
14 years 22 days ago
Power estimation for architectural exploration of HW/SW communication on system-level buses
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
SACMAT
2006
ACM
14 years 2 months ago
PRIMA: policy-reduced integrity measurement architecture
We propose an integrity measurement approach based on information flow integrity, which we call the Policy-Reduced Integrity Measurement Architecture (PRIMA). The recent availabi...
Trent Jaeger, Reiner Sailer, Umesh Shankar
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
14 years 12 days ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan
GI
2004
Springer
14 years 1 months ago
Dynamical Vertical Integration of Distributed Java Components Using an Architecture Model
Abstract: A key idea of architecture is the description of components and their connections. This information can be extended to define the horizontal and vertical distribution of...
Alexander Prack, Ulf Schreier
GECCO
2006
Springer
253views Optimization» more  GECCO 2006»
14 years 2 days ago
A novel approach to optimize clone refactoring activity
Achieving a high quality and cost-effective tests is a major concern for software buyers and sellers. Using tools and integrating techniques to carry out low cost testing are chal...
Salah Bouktif, Giuliano Antoniol, Ettore Merlo, Ma...