379 search results - page 25 / 76 » Optimal loop parallelization for maximizing iteration-level ... |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
FPL
2003
Springer
14 years 19 days ago
2003
Springer
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
PPOPP
2005
ACM
14 years 29 days ago
2005
ACM
We want to perform compile-time analysis of an SPMD program and place barriers in it to synchronize it correctly, minimizing the runtime cost of the synchronization. This is the b...
PLDI
2005
ACM
14 years 29 days ago
2005
ACM
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
ISCAPDCS
2001
13 years 8 months ago
2001
-Multi-dimensional applications, such as image processing and seismic analysis, usually require the optimized performance obtained from instruction-level parallelism. The critical ...