Sciweavers

711 search results - page 100 / 143
» Optimal placement by branch-and-price
Sort
View
CODES
2000
IEEE
14 years 7 days ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
COLT
2010
Springer
13 years 5 months ago
Active Learning on Trees and Graphs
We investigate the problem of active learning on a given tree whose nodes are assigned binary labels in an adversarial way. Inspired by recent results by Guillory and Bilmes, we c...
Nicolò Cesa-Bianchi, Claudio Gentile, Fabio...
ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
14 years 1 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
DAC
2002
ACM
14 years 8 months ago
River PLAs: a regular circuit structure
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
Fan Mo, Robert K. Brayton
DAC
2004
ACM
14 years 8 months ago
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
This paper presents the Quantum-Dot Cellular Automata (QCA) physical design problem, in the context of the VLSI physical design problem. The problem is divided into three subprobl...
Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dy...