1156 search results - page 211 / 232 » Optimal scheduling of task graphs on parallel systems |
136
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ASPLOS
2010
ACM
15 years 11 months ago
2010
ACM
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
137
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FPL
2009
Springer
15 years 9 months ago
2009
Springer
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
131
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EMSOFT
2008
Springer
15 years 6 months ago
2008
Springer
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The ...
133
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ISCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
142
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ITC
1999
IEEE
15 years 9 months ago
1999
IEEE
A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high...