862 search results - page 81 / 173 » Optimal task placement to improve cache performance |
168
Voted
ICPPW
2007
IEEE
15 years 10 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
159
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ESTIMEDIA
2007
Springer
15 years 10 months ago
2007
Springer
Today’s embedded applications often consist of multiple concurrent tasks. These tasks are decomposed into subtasks which are in turn assigned and scheduled on multiple different...
127
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DATE
1998
IEEE
15 years 8 months ago
1998
IEEE
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
151
Voted
ISLPED
2010
ACM
15 years 4 months ago
2010
ACM
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
134
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ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...