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DSD
2009
IEEE
124views Hardware» more  DSD 2009»
14 years 2 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
SAC
2004
ACM
14 years 1 months ago
DSPxPlore: design space exploration methodology for an embedded DSP core
High mask and production costs for the newest CMOS silicon technologies increase the pressure to develop hardware platforms useable for different applications or variants of the s...
Christian Panis, Ulrich Hirnschrott, Gunther Laure...
JUCS
2006
112views more  JUCS 2006»
13 years 7 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 11 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
DATE
2006
IEEE
149views Hardware» more  DATE 2006»
14 years 1 months ago
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures ha...
Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee...