96 search results - page 16 / 20 » Optimization of Combinational Logic Circuits Based on Compat... |
ATS
2009
IEEE
13 years 5 months ago
2009
IEEE
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
ICCAD
1991
IEEE
13 years 11 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...