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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 10 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
JFR
2006
108views more  JFR 2006»
15 years 4 months ago
Learning in a hierarchical control system: 4D/RCS in the DARPA LAGR program
The Defense Applied Research Projects Agency (DARPA) Learning Applied to Ground Vehicles (LAGR) program aims to develop algorithms for autonomous vehicle navigation that learn how...
James S. Albus, Roger Bostelman, Tommy Chang, Tsai...
CODES
2009
IEEE
15 years 11 months ago
FlexRay schedule optimization of the static segment
The FlexRay bus is the prospective automotive standard communication system. For the sake of a high flexibility, the protocol includes a static time-triggered and a dynamic event...
Martin Lukasiewycz, Michael Glaß, Jürge...
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
ESTIMEDIA
2008
Springer
15 years 6 months ago
A framework for memory-aware multimedia application mapping on chip-multiprocessors
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasric...