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ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 9 days ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
13 years 11 months ago
Platform-based design of wireless sensor networks for industrial applications
We present a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN). While the method is quite general, we use extensively an exa...
Alvise Bonivento, Luca P. Carloni, Alberto L. Sang...
ISSS
1995
IEEE
87views Hardware» more  ISSS 1995»
13 years 11 months ago
Industrial experience using rule-driven retargetable code generation for multimedia applications
The increasing usage of Application Specific Instruction Set Processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicat...
Clifford Liem, Pierre G. Paulin, Marco Cornero, Ah...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 11 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
LCTRTS
1999
Springer
13 years 11 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...