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155
Voted
CODES
2007
IEEE
15 years 10 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
LCTRTS
2007
Springer
15 years 10 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
156
Voted
CODES
2006
IEEE
15 years 9 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
140
Voted
OOPSLA
2004
Springer
15 years 9 months ago
Method-level phase behavior in java workloads
Java workloads are becoming more and more prominent on various computing devices. Understanding the behavior of a Java workload which includes the interaction between the applicat...
Andy Georges, Dries Buytaert, Lieven Eeckhout, Koe...
CASES
2003
ACM
15 years 9 months ago
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
This paper presents a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-m...
Sumesh Udayakumaran, Rajeev Barua