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» Optimizations for LTL Synthesis
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EMSOFT
2007
Springer
15 years 10 months ago
A communication synthesis infrastructure for heterogeneous networked control systems and its application to building automation
In networked control systems the controller of a physicallydistributed plant is implemented as a collection of tightlyinteracting, concurrent processes running on a distributed ex...
Alessandro Pinto, Luca P. Carloni, Alberto L. Sang...
CODES
2005
IEEE
15 years 9 months ago
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs
This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer man...
Hyunok Oh, Nikil D. Dutt, Soonhoi Ha
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
15 years 9 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
15 years 9 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
RTSS
1998
IEEE
15 years 8 months ago
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
Inki Hong, Gang Qu, Miodrag Potkonjak, Mani B. Sri...