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CORR
2010
Springer
89views Education» more  CORR 2010»
13 years 7 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 8 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
ERSA
2006
105views Hardware» more  ERSA 2006»
13 years 8 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
DAC
2000
ACM
14 years 8 months ago
Depth optimal incremental mapping for field programmable gate arrays
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
Jason Cong, Hui Huang
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 4 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He