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» Optimized self-tuning for circuit aging
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ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
16 years 16 days ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
DATE
2009
IEEE
114views Hardware» more  DATE 2009»
16 years 12 days ago
Hardware aging-based software metering
Abstract—Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property a...
Foad Dabiri, Miodrag Potkonjak
ICVS
2001
Springer
15 years 10 months ago
Compiling SA-C Programs to FPGAs: Performance Results
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...
Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hamm...
DATE
2009
IEEE
145views Hardware» more  DATE 2009»
16 years 12 days ago
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...
Kai-Chiang Wu, Diana Marculescu