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» Optimizing Design for Variability Using Traceability Links
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DAC
2005
ACM
14 years 9 months ago
A new canonical form for fast boolean matching in logic synthesis and verification
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
Afshin Abdollahi, Massoud Pedram
WCE
2007
13 years 9 months ago
Stochastic Urban Rapid Transit Network Design
— The rapid transit network design problem considers at upper level the list of potential transit corridors and stations to design the network as a discrete space of alternatives...
Carlos Bouza, Gemayzel Bouza, Ángel Mar&iac...
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
14 years 23 days ago
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
Nazanin Mansouri, Ranga Vemuri
HICSS
2008
IEEE
128views Biometrics» more  HICSS 2008»
14 years 2 months ago
Service Composition Language to Unify Simulation and Optimization of Supply Chains
Proposed and developed is the language Service Composition (SC) CoJava, which extends the programming language Java with (1) a modular service composition framework; (2) an extens...
Alexander Brodsky, Malak Al-Nory, Hadon Nash
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 2 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic