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» Optimizing Dynamic Binary Translation for SIMD Instructions
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CASES
2010
ACM
13 years 6 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 2 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
IPPS
2006
IEEE
14 years 2 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
DAC
2011
ACM
12 years 8 months ago
Process-level virtualization for runtime adaptation of embedded software
Modern processor architectures call for software that is highly tuned to an unpredictable operating environment. Processlevel virtualization systems allow existing software to ada...
Kim M. Hazelwood
CASES
2004
ACM
14 years 1 months ago
A post-compiler approach to scratchpad mapping of code
ScratchPad Memories (SPMs) are commonly used in embedded systems because they are more energy-efficient than caches and enable tighter application control on the memory hierarchy...
Federico Angiolini, Francesco Menichelli, Alberto ...