1276 search results - page 11 / 256 » Optimizing Hierarchical Schedules for Improved Control Perfo... |
DAC
1998
ACM
13 years 11 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
DEXAW
1999
IEEE
13 years 11 months ago
1999
IEEE
Robotic tape libraries (RTLs) currently enjoy a prominent place in the storage market, with a reported average annual growth rate approaching 34%, primarily due to their low cost ...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
PLDI
2005
ACM
14 years 29 days ago
2005
ACM
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...
EMSOFT
2007
Springer
14 years 1 months ago
2007
Springer
Most recent embedded systems use caches to improve their average performance. Current timing analyses are able to compute safe timing guarantees for these systems, if tasks are ru...