244 search results - page 15 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...