244 search results - page 22 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
113
Voted
DATE
2010
IEEE
15 years 8 months ago
2010
IEEE
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
136
Voted
LCPC
2000
Springer
15 years 7 months ago
2000
Springer
State-of-the-art run-time systems are a poor match to diverse, dynamic distributed applications because they are designed to provide support to a wide variety of applications, with...
144
Voted
CLUSTER
2007
IEEE
15 years 10 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
149
Voted
ISLPED
2004
ACM
15 years 9 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
163
Voted
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
15 years 7 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....