277 search results - page 45 / 56 » Optimizing Power Consumption in Large Scale Storage Systems |
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Random access memory (RAM) is tightly-constrained in many embedded systems. This is especially true for the least expensive, lowest-power embedded systems, such as sensor network ...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
BWCCA
2010
13 years 2 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...