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» Optimizing Resource Utilization Using Transformations
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ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 1 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
MST
2002
169views more  MST 2002»
13 years 8 months ago
Bulk Synchronous Parallel Algorithms for the External Memory Model
Abstract. Blockwise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is f...
Frank K. H. A. Dehne, Wolfgang Dittrich, David A. ...
RTS
2008
134views more  RTS 2008»
13 years 7 months ago
On earliest deadline first scheduling for temporal consistency maintenance
A real-time object is one whose state may become invalid with the passage of time. A temporal validity interval is associated with the object state, and the real-time object is te...
Ming Xiong, Qiong Wang, Krithi Ramamritham
ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
14 years 3 months ago
On Parallelization of a Video Mining System
As digital video data becomes more pervasive, mining information from multimedia data becomes increasingly important. Although researches in multimedia mining area have shown grea...
Wenlong Li, Eric Li, Nan Di, Carole Dulong, Tao Wa...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 5 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He