5 search results - page 1 / 1 » Optimizing Stresses for Testing DRAM Cell Defects Using Elec... |
DATE
2003
IEEE
14 years 4 months ago
2003
IEEE
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
ATS
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract: Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modi...
ATS
2003
IEEE
14 years 4 months ago
2003
IEEE
Abstract: As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates th...
ATS
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
MTDT
2003
IEEE
14 years 4 months ago
2003
IEEE
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...