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ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
14 years 1 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
CDC
2009
IEEE
154views Control Systems» more  CDC 2009»
14 years 1 months ago
On the optimal design of structured feedback gains for interconnected systems
— We consider the design of optimal static feedback gains for interconnected systems subject to architectural constraints on the distributed controller. These constraints are in ...
Makan Fardad, Fu Lin, Mihailo R. Jovanovic
DAC
2001
ACM
14 years 10 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
ICCAD
1997
IEEE
91views Hardware» more  ICCAD 1997»
14 years 1 months ago
Interconnect layout optimization under higher-order RLC model
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...
Jason Cong, Cheng-Kok Koh
ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
14 years 2 months ago
Inductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
Magdy A. El-Moursy, Eby G. Friedman