1912 search results - page 13 / 383 » Optimizing interconnection policies |
CSREAESA
2006
13 years 10 months ago
2006
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of...
ISPD
2000
ACM
14 years 1 months ago
2000
ACM
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...
SIAMCO
2011
13 years 4 months ago
2011
Given a nominal plant, together with a fixed neighborhood of this plant, the problem of robust stabilization is to find a controller that stabilizes all plants in that neighborh...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...