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    ICCAD
    1996
    IEEE
    106views Hardware» more  ICCAD 1996»
    Buffered Steiner tree construction with wire sizing for interconnect layout optimization
    15 years 7 months ago
    Buffered Steiner tree construction with wire sizing for interconnect layout optimization
    Download  www.cs.ucr.edu
    Takumi Okamoto, Jason Cong
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    ISCAS
    1993
    IEEE
    77views Hardware» more  ISCAS 1993»
    Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort
    15 years 7 months ago
    Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort
    Download  www.suryatech.com
    Kumar Venkat
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    ICCAD
    1995
    IEEE
    77views Hardware» more  ICCAD 1995»
    Optimal wiresizing for interconnects with multiple sources
    15 years 6 months ago
    Optimal wiresizing for interconnects with multiple sources
    Download  cadlab.cs.ucla.edu
    Jason Cong, Lei He
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    NOCS
    2010
    IEEE
    115views Computer Networks» more  NOCS 2010»
    Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized Computing
    15 years 1 months ago
    Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized Computing
    Download  www.minatec.org
    Keren Bergman
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    TPDS
    2010
    84views more  TPDS 2010»
    Communication Requirements and Interconnect Optimization for High-End Scientific Applications
    15 years 1 months ago
    Communication Requirements and Interconnect Optimization for High-End Scientific Applications
    Download  bebop.cs.berkeley.edu
    Shoaib Kamil, Leonid Oliker, Ali Pinar, John Shalf
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