1912 search results - page 212 / 383 » Optimizing interconnection policies |
113
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
158
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ARC
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
117
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MICRO
2006
IEEE
15 years 10 months ago
2006
IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
241
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BWCCA
2010
14 years 11 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
123
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ICML
2006
IEEE
16 years 5 months ago
2006
IEEE
How should a reinforcement learning agent act if its sole purpose is to efficiently learn an optimal policy for later use? In other words, how should it explore, to be able to exp...