2703 search results - page 117 / 541 » Optimizing memory transactions |
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
FOCS
1998
IEEE
14 years 1 months ago
1998
IEEE
The speed of many computations is limited not by the number of arithmetic operations but by the time it takes to move and rearrange data in the increasingly complicated memory hie...
ACMMSP
2006
ACM
14 years 2 months ago
2006
ACM
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
ICPP
1998
IEEE
14 years 1 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...