2703 search results - page 127 / 541 » Optimizing memory transactions |
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
ISCA
2000
IEEE
14 years 1 months ago
2000
IEEE
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
CAV
2010
Springer
14 years 25 days ago
2010
Springer
Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a chal...
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
EDBT
2008
ACM
14 years 9 months ago
2008
ACM
Data Stream Management Systems (DSMSs) must support optimized execution scheduling of multiple continuous queries on massive, and frequently bursty, data streams. Previous approac...