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ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 3 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
MICRO
2007
IEEE
139views Hardware» more  MICRO 2007»
14 years 4 months ago
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
Onur Mutlu, Thomas Moscibroda
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
14 years 2 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...
IWMM
2010
Springer
140views Hardware» more  IWMM 2010»
13 years 12 months ago
Parametric inference of memory requirements for garbage collected languages
The accurate prediction of program's memory requirements is a critical component in software development. Existing heap space analyses either do not take deallocation into ac...
Elvira Albert, Samir Genaim, Miguel Gómez-Z...
SOSP
1997
ACM
13 years 11 months ago
Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network
Low-latency remote-write networks, such as DEC’s Memory Channel, provide the possibility of transparent, inexpensive, large-scale shared-memory parallel computing on clusters of...
Robert Stets, Sandhya Dwarkadas, Nikos Hardavellas...