2703 search results - page 200 / 541 » Optimizing memory transactions |
130
Voted
DATE
2010
IEEE
15 years 7 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
107
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DAC
1996
ACM
15 years 6 months ago
1996
ACM
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer ...
157
Voted
JSSPP
1997
Springer
1997
Springer
An Experimental Evaluation of Processor Pool-Based Scheduling for Shared-Memory NUMA Multiprocessors
15 years 6 months ago
In this paper we describe the design, implementation and experimental evaluation of a technique for operating system schedulers called processor pool-based scheduling [51]. Our tec...
119
Voted
FPGA
2000
ACM
15 years 6 months ago
2000
ACM
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
131
Voted
BDA
2003
15 years 4 months ago
2003
Pervasive computing introduces data management requirements that must be tackled in a growingvariety of lightweight computing devices. Personal folders on chip, networks of sensor...