Sciweavers

2703 search results - page 77 / 541
» Optimizing memory transactions
Sort
View
CAL
2008
13 years 7 months ago
Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. Howev...
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, ...
VLDB
1997
ACM
104views Database» more  VLDB 1997»
14 years 27 days ago
Integrating Reliable Memory in Databases
Abstract. Recent results in the Rio project at the University of Michigan show that it is possible to create an area of main memory that is as safe as disk from operating system cr...
Wee Teck Ng, Peter M. Chen
CODES
2003
IEEE
14 years 2 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
WWW
2004
ACM
14 years 9 months ago
A smart hill-climbing algorithm for application server configuration
The overwhelming success of the Web as a mechanism for facilitating information retrieval and for conducting business transactions has led to an increase in the deployment of comp...
Bowei Xi, Zhen Liu, Mukund Raghavachari, Cathy H. ...
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
14 years 13 days ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...