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MICRO
2003
IEEE
96views Hardware» more  MICRO 2003»
14 years 1 months ago
Scalable Hardware Memory Disambiguation for High ILP Processors
This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows...
Simha Sethumadhavan, Rajagopalan Desikan, Doug Bur...
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
14 years 1 months ago
Memory System Connectivity Exploration
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
ICASSP
2010
IEEE
13 years 8 months ago
Maximizing the lifetime of clusters with Slepian-Wolf coding
In this paper, we propose an iteration-free algorithm to find the optimal configuration, including transmit power and source coding rates, to maximize the lifetime of a cluster ...
Tianqi Wang, Wendi Rabiner Heinzelman, Alireza Sey...
ICIC
2007
Springer
13 years 10 months ago
Parameter Tuning for Buck Converters Using Genetic Algorithms
The buck converter is one of DC/DC converters that are often used as power supplies. This paper presents parameter tuning methods to obtain circuit element values for the buck conv...
Young-Kiu Choi, Byung-Wook Jung
ICCAD
2008
IEEE
116views Hardware» more  ICCAD 2008»
14 years 5 months ago
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
Ranko Sredojevic, Vladimir Stojanovic