2048 search results - page 255 / 410 » Optimizing pipelines for power and performance |
CN
2002
13 years 8 months ago
2002
In todays IP networks most of the network control and management tasks are performed at the end points. As a result, many important network functions cannot be optimized due to la...
IPCCC
2006
IEEE
14 years 2 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
ASIAN
2004
Springer
14 years 1 months ago
2004
Springer
Designing custom solutions has been central to meeting a range of stringent and specialized needs of embedded computing, along such dimensions as physical size, power consumption, ...