2048 search results - page 279 / 410 » Optimizing pipelines for power and performance |
CVPR
2011
IEEE
12 years 12 months ago
2011
IEEE
Spatial Pyramid Representation (SPR) is a widely used method for embedding both global and local spatial information into a feature, and it shows good performance in terms of gene...
CODES
2004
IEEE
13 years 12 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
DSN
2003
IEEE
14 years 1 months ago
2003
IEEE
Processor caches already play a critical role in the performance of today’s computer systems. At the same time, the data integrity of words coming out of the caches can have ser...