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» Optimizing pipelines for power and performance
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PLDI
2003
ACM
14 years 1 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
IAT
2009
IEEE
14 years 2 months ago
Cluster-Swap: A Distributed K-median Algorithm for Sensor Networks
In building practical sensor networks, it is often beneficial to use only a subset of sensors to take measurements because of computational, communication, and power limitations....
Yoonheui Kim, Victor R. Lesser, Deepak Ganesan, Ra...
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
12 years 11 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
TWC
2008
159views more  TWC 2008»
13 years 7 months ago
Resource allocation for spectrum underlay in cognitive radio networks
A resource allocation framework is presented for spectrum underlay in cognitive radio networks. We consider both interference constraints for primary users and quality of service (...
Long Bao Le, Ekram Hossain
DAC
2009
ACM
14 years 9 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert