Sciweavers

954 search results - page 7 / 191
» Optimizing power and performance for reliable on-chip networ...
Sort
View
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
14 years 1 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
ASPDAC
2010
ACM
143views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Optimizing power and performance for reliable on-chip networks
Aditya Yanamandra, Soumya Eachempati, Niranjan Sou...
DAC
2005
ACM
13 years 9 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...
MOBICOM
1999
ACM
14 years 1 days ago
Optimizing the End-to-End Performance of Reliable Flows Over Wireless Links
We present the results of a performance evaluation of link layer error recovery over wireless links. Our analysis is based upon a case study of the circuit-switched data service i...
Reiner Ludwig, Almudena Konrad, Anthony D. Joseph
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 11 months ago
Thermal and Power Integrity Based Power/Ground Networks Optimization
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Pin...