366 search results - page 69 / 74 » Optimizing the Evaluation of XPath Using Description Logics |
FPGA
2010
ACM
13 years 8 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
SIGCOMM
2004
ACM
14 years 1 months ago
2004
ACM
A detailed understanding of the many facets of the Internet’s topological structure is critical for evaluating the performance of networking protocols, for assessing the effecti...
DLOG
2006
13 years 9 months ago
2006
Highly optimized reasoning support for Description Logics (DLs) has been developed during the past years. This paper presents our efforts to develop a reasoner suitable for mobile ...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...