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» Optimizing the FPGA Implementation of HRT Systems
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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 3 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
INFOCOM
2010
IEEE
13 years 7 months ago
Leaping Multiple Headers in a Single Bound: Wire-Speed Parsing Using the Kangaroo System
—More fundamental than IP lookups and packet classification in routers is the extraction of fields such as IP Dest and TCP Ports that determine packet forwarding. While parsing...
Christos Kozanitis, John Huber, Sushil Singh, Geor...
CODES
2009
IEEE
14 years 18 days ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 10 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang