1990 search results - page 50 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ISSS
1996
IEEE
13 years 11 months ago
1996
IEEE
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
EUROPAR
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. Hardware Transactional Memory (HTM) gives software developers the opportunity to write parallel programs more easily compared to any previous programming method, and yiel...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
With the widespread use of embedded devices such as PDAs, printers, game machines, cellular telephones, achieving high performance demands an optimized operating system (OS) that ...
CASES
2004
ACM
14 years 1 months ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...